According to accounts provided to IT Brand Pulse, the CXL 2.x chip remains available, but raises questions about the CXL 3.x switch Marvell announced and the industry’s path to large memory fabrics.

Several sources attending the Global OCP Summit told IT Brand Pulse that Marvell intends to continue offering its current CXL switch chip but does not plan to offer future generations, instead directing resources toward UALink and/or NVLink switching products. The accounts concern CXL switch development and don’t suggest that Marvell is withdrawing its CXL memory-expansion controllers, near-memory accelerators, retimers or other CXL-related offerings.

If accurate, the reported Marvell roadmap change raises an important question for the CXL ecosystem: who will supply the next generation of switch silicon needed to move beyond today’s production platforms toward larger, more flexible memory fabrics?

Reconciling the reports with Marvell’s previous announcement

On March 17, 2026, Marvell announced, “The Marvell Structera S 30260 CXL switch is expected to begin sampling to customers in calendar Q3 2026. The Structera S 20256 CXL 2.0 switch is currently in production.”

This raises critical questions and answers that shape the impact of the reported decision:

• Does the reported decision include the announced 30260 or does it refer to generations beyond the 30260? Continuing to sell the 30260 is vastly different from discontinuing it. Which leads to a question about sampling to customers in calendar Q3 2026.
• Did sampling occur for the 30260? If the reported decision prevents that 30260 from sampling, it represents a massive roadblock for the timeline of 3.x CXL data center switch architectures. The gap between existing production-grade silicon and next-generation CXL fabrics would be huge.

NVIDIA’s $2 billion investment in Marvell changed the equation

The overall rationale for a shift is the larger market opportunity with stronger ecosystem support.

In March 2026, NVIDIA and Marvell announced an expanded partnership under which Marvell would provide custom XPUs and NVLink Fusion-compatible scale-up networking. NVIDIA also announced a $2 billion investment in Marvell. Separately, Marvell publicly described development of NVLink-compatible switches alongside PCIe, UALink and ESUN products.

This collaboration changes the investment equation. NVIDIA is giving partners a path to build products around its preferred architecture, offering a stronger incentive to commit engineering resources. More broadly, NVLink, PCIe and UALink switching could give Marvell access to larger opportunities supported by broader platform requirements and ecosystem commitments of their respective customers and partners.

The gap between CXL 2.0 and 3.0: What it means to large fabrics

The availability of a production-grade CXL 2.0-based product is critical to system builders and customers because it supports switching and pooled memory.

CXL 3.0 expands the architecture with multi-level switching, enhanced sharing and coherency, peer-to-peer communication and greater fabric scalability. Later 3.x capabilities further develop that foundation.

Without 3.x-based products, CXL system vendors and buyers have limited options when designing larger memory pools. And their roadmap will now include the need to design-in a new CXL switch from a supplier like Panmnesia, or qualifying an alternative fabric architecture.

An opening for Panmnesia

Panmnesia is developing advanced CXL switch ASICs. In April 2026, the company announced the supply of pre-release PCIe 6.4/CXL 3.2 fusion-switch silicon, including port-based routing. Its public website also offers access to pre-release silicon.

Its recent research collaboration with Meta provides another promising signal. Researchers from Panmnesia and Meta co-authored “One-chip-like datacenter design enabled by CXL-based scale-up fabrics,” published in Nature Reviews Electrical Engineering in August 2026 and highlighted by Panmnesia in September. The work describes an architecture that uses CXL fabrics and dedicated hardware to extend tightly coupled computing beyond individual servers and racks.

Collaboration with researchers from one of the world’s largest infrastructure operators goes a long way toward validating the relevance of Panmnesia technical direction and strengthening confidence in the potential of its products. It connects the company’s fabric ambitions with the challenges hyperscalers actually face. That is encouraging.

But even with promising silicon, filling the ecosystem gap would take time. Broad integration around a new switch chip would likely unfold over years. System vendors and software partners would need to integrate boards, firmware, fabric management and orchestration; verify interoperability with host processors and memory devices; and qualify performance, security and failure recovery under customer workloads.

The outlook A sharper focus on DDR4 reuse and memory pooling

The near-term impact of the reported halt to Marvell’s announced CXL 3.0 switch development would be a laser focus by the CXL industry on three applications: enabling DDR4 reuse inside AI servers, expanding memory capacity with CXL add-in memory cards in KV cache servers, and sharing memory through pooling systems outside AI servers. The second application combines high capacity memory with the opportunity to reuse DDR4 when building these servers.

Reusing DDR – Enabling Reuse of DDR4 is the killer app for CXL today. New AI servers do not natively support an estimated 180 million installed DDR4 RDIMMs available for reuse. If cloud service providers and enterprises can’t reuse them, they’ll have to conservatively spend $250 billion on new DDR5 RDIMMs at $30/GB. CXL memory controllers support DDR4 making them the keys that unlock the reuse of DDR4 in new servers.

KV Cache Servers – Vendors like Penguin Solutions are using CXL add-in memory cards to expand the memory available to servers that store and serve the key-value cache generated during AI inference. This provides high capacity memory for growing KV cache requirements. Cards equipped with DDR4-compatible CXL memory controllers can also reuse qualified DDR4 RDIMMs, allowing customers to build KV cache servers with existing memory assets and reduce the amount of new memory they need to purchase.

Memory Pooling – The recent announcement from Liqid about its role in Abaco provides a concrete example of why customers want memory pooling and why vendors are building it with CXL 2.0 today. Designed by Micron for Pacific Northwest National Laboratory, Abaco addresses AI and scientific workloads whose memory requirements exceed the capacity of individual servers. Liqid describes a configuration with up to 160 TB of DDR5 pooled across as many as 16 hosts, supported by its CXL 2.0 fabric and orchestration software. The customer motivation is clear: make larger datasets available in memory and allocate capacity where workloads need it, rather than buying additional servers simply to obtain more DRAM. In our view, Abaco demonstrates that useful memory pooling systems need not wait for CXL 3.x switches.

The Bottom Line

The bottom line is the equation has changed. If the reported roadmap decision is confirmed, directing Marvell’s resources toward larger accelerator-switching markets would be a logical business decision given its scale and competing investment opportunities.

Furthermore, Marvell will be able to recoup their investment in the acquisition of XConn because we estimate 80% of the engineering foundation behind a CXL switch would likely carry over to a PCIe switch with a strong overlap in physical interfaces, PCIe functionality and switching infrastructure.  We estimate a quarter to a third of the engineering foundation can also be reused for UALink or NVLink-compatible switches, including reusable design blocks, tools and engineering methods.

We predict Panmnesia will be a good fit to carry the flag for CXL 3.x switch chips going forward. The company is a focused startup and doesn’t need the large market size that Marvell needs to justify the cost of development, and if Panmnesia can get a product to market, demand for advanced memory fabrics is there.

Editor’s Note

IT Brand Pulse reached out to Marvell Technology executives on Friday, October 16, 2026, with a draft of this article to request comment or clarification on the reported changes to their CXL switch roadmap. Marvell did not respond to multiple requests for comment prior to our publication deadline. This article will be updated to reflect any statement Marvell provides in the future.